In recent large scale integrations (LSIs), a built-in self-test (BIST) circuit (hereinafter, referred to as a BIST circuit) is frequently used for testing a random access memory (RAM) integrated in an LSI, as a unit test for the LSI.
An LSI provided with BIST circuit includes a test control circuit that generates an address and data, and a control signal for testing a RAM with minimum settings supplied from the outside of the LSI. An LSI provided with a BIST circuit can automatically test a RAM using a test control circuit and the BIST circuit, and can store test results for the RAM in the BIST circuit. The pass or fail determination for the RAM can be made afterward by reading the test results stored in the BIST circuit from the outside.
As described above, by using the test control circuit and the BIST circuit in an LSI unit test, the time of the test and the number of patterns provided to the LSI can be significantly reduced, as compared to techniques wherein all of test patterns are provided to a RAM from the outside of the LSI and the results are read.
Generally, a 1 Read-Write-RAM (1RW-RAM) is used for a RAM provided in an LSI, such as a central processing unit (CPU). A 1RW-RAM uses a pair of address and data for accessing to the RAM for both read and write operations, and thus a read operation cannot be executed simultaneously with a write operation.
In recent years, in addition to a 1RW-RAM, a 1 Read-1 Write-RAM (1R1W-RAM) is provided in a CPU. A 1R1W-RAM uses two independent pairs of an address and data for accessing to the RAM for a read operation and a write operation, and hence a read operation can be executed simultaneously with a write operation.
FIG. 6 is a diagram illustrating an exemplary configuration of an integrated circuit 100 including a 1RW-RAM circuit 200 with RAM-GIST, and FIG. 7 is a diagram illustrating an exemplary configuration of an integrated circuit 110 including a 1R1 W-RAM circuit 210 with RAM-BIST.
In FIGS. 6 and 7, only address and data signals used for a test are illustrated, and control signals for a write operation and/or a read operation from a test control circuits 800 and 810 to RAMs 300 and 310, and a control signal to a result register 470b are omitted. A LSI tester for setting the test control circuits 800 and 810, and signals between the LSI tester and the test control circuits 800 and 810 are also omitted.
As illustrated in FIG. 6, the test control circuit 800 outputs a pair of address and data to the 1RW-RAM circuit 200. In the 1RW-RAM circuit 200, the address and data that are output are used, as a write address and write data for a write operation, while being used as a read address and an expected value for verifying a read data for the read operation.
In contrast, as illustrated in FIG. 7, the test control circuit 810 outputs two pairs of address and data for a write operation and a read operation to the 1R1W-RAM circuit 210. The write address and write data are used as a write address and write data for a write operation, and the read address and read data are used as a read address and a read expected value for a read operation.
In this manner, since the test control circuit 810 provides separate addresses and data for a write operation and a read operation, the integrated circuit 110 depicted in FIG. 7 can execute simultaneous read and write operation test, which is a unique operation of the 1R1W-RAM.
In FIGS. 6 and 7, when a read operation is made, data read from the 1RW-RAM 300 and 1R1W-RAM 310 is compared against an expected value in a comparator 470a, and the result of the comparison is stored in the result register 470b. 
Next, the integrated circuit 100 depicted in FIG. 6 will be described in detail.
FIG. 8 is a diagram illustrating a detailed exemplary configuration of the integrated circuit 100 including the 1RW-RAM 200, and FIG. 9 is a flowchart illustrating an exemplary operation of the 1RW-RAM circuit 200.
FIG. 10 is a flowchart illustrating an exemplary operation of a march test on the test control circuit 800 for the 1RW-RAM, and FIG. 11 is a diagram illustrating an exemplary operation of the 1RW-RAM circuit 200 in the march test.
In (a) of FIG. 11, the vertical axis indicates address in a 1RW-RAM 300, whereas the horizontal axis indicates time. Further, “W0” and “W1” indicate write of 0 data and 1 data, respectively, “R0” and “R1” indicate read of 0 data and 1 data, respectively. The numbers (1) to (7) in the timing chart in (b) of FIG. 11 indicate corresponding signals or registers in FIG. 8.
An LSI generally includes multiple 1RW-RAMs, and as depicted in FIG. 8, the integrated circuit 100 includes n (n is an integer of 1 or greater) 1RW-RAM circuits 200-1 to 200-n, and a pattern generator (PG) 800 for the 1RW-RAMs, as an example of a test control circuit, for example. Hereinafter, any one of the 1RW-RAM circuits may be simply referred to as a 1RW-RAM circuit 200.
In the integrated circuit 100, a single PG 8 for a 1RW-RAM (hereinafter, simply referred to as a PG) 800 is connected to the multiple 1RW-RAM circuits 200, and test information is output from the PG 800 to each of the 1RW-RAM circuits 200.
The 1RW-RAM circuit 200 includes a 1RW-RAM 300 to be tested, and a BIST circuit 400A added to the 1RW-RAM 300.
Here, the 1RW-RAM 300 illustrated in FIG. 8 includes a configuration of 1024 words×72 bits, and includes a 10-bits address terminal “AD”, a 1-bit write enable terminal “WE”, and 72-bits data input terminal and data output terminal.
Further, a write operation and a read operation in the 1RW-RAM 300 is executed one clock after when input signals, i.e., an address signal, a write enable signal, and a data signal, are supplied from the test control circuit 800.
The 1RW-RAM 300 is a RAM which uses an input address for both a write operation and a read operation, as described above, and for an address input to the “AD” terminal, i.e., a cell selected by a signal, write is executed when a signal input to the “WE” terminal is “H”, and read is executed when “L”. Thus, as described above, the 1RW-RAM 300 cannot execute a write and a read simultaneously.
The PG 800 generates an “address” signal, a “data” signal, a “we” signal, and an “le” signal, and supplies them to the 1RW-RAM circuit 200 as test information.
The “address” signal is an address signal for selecting a particular cell in a particular memory cell in the 1RW-RAM 300, and the “data” signal is write data to be written to the memory cell and is also an expected value to be compared against data read from the memory cell. The “we” signal is a write enable signal for enabling the write operation, and the “le” signal is a load enable signal for controlling a comparison between read data from the 1RW-RAM 300 and the expected value.
The BIST circuit 400A includes registers 410 to 460 that store the test information supplied from the PG 800 and a data receiver (DRCV) 470.
The DRCV 470 includes a comparator 470a and a result register 470b illustrated in FIG. 6. The comparator 470a compares data read from the 1RW-RAM 300 and an expected value stored in the WD_delayed 450, and the result register 470b stores a result of the comparison by the comparator 470a. 
Hereinafter, an exemplary operation of the 1RW-RAM circuit 200 will be described with reference to FIG. 9.
Firstly, test information is generated by the PG 800 and is supplied to the 1RW-RAM circuit 200, and a “we” signal is stored in a +WE 410, an “address” signal in an AD 420, a “data” signal in a WD 430, the “le” signal in a +LE 440 (Step S110).
Next, in the BIST circuit 400A, a “WD” signal which is an output from the WD 430 is stored in a WD_delayed 450, and a “+LE” signal which is an output from the +LE 440 is stored in +LE_delayed 460 (Step S120).
Also in the BIST circuit 400A, it is determined whether or not a “+WE” signal which is an output from the +WE 410 is “H”, e.g., “1” (Step S130). If the “+WE” signal is “H” (the Yes route from Step S130), the “WD” signal from the WD 430 is written to the cell in the 1RW-RAM 300 selected by the data stored in the AD 420, i.e., the “AD” signal which is an output from the AD 420 (Step S140). Otherwise, if the “+WE” signal is “L”, e.g., “0” (the No route from Step S130), the cell in the 1RW-RAM 300 selected by the “AD” signal from the AD 420 is read (Step S150).
Subsequently, in the BIST circuit 400A, it is determined whether or not the value of a “+en” signal which is an output from the +LE_delayed 460 is “H” (Step S160). If the “+en” signal is “H” (the Yes route from Step S160), a “Read data” signal which is read data from the 1RW-RAM 300 is compared against a “WD_delayed” signal which is an output from the WD_delayed 450, i.e., the expected value, in the DRCV 470, and the result is saved (Step S170). Otherwise, if the “+en” signal is “L” (the No route from Step S160), the processing in Step S170 is deterred.
If “+WE” signal from the +WE 410 is “H”, the “+LE” signal from the +LE 440 is controlled from outside, e.g., in the PG 800, not so as to assume “H”.
The processing in Step S120 is executed to synchronize the timing of the expected value supplied from the PG 800 with the timing of the “Read_data” signal from the 1RW-RAM 300, when the cell in the 1RW-RAM 300 is read in Step S150.
In other words, the WD_delayed 450 is a register that delays the “WD” signal from the WD 430 by one clock cycle required for the read operation of the 1RW-RAM 300, for the comparison by the DRCV 470 in Step S170. Similarly, the +LEdelayed 460 is a register that delays the “+LE” signal from the +LE 440 by one clock cycle, in order to wait for the result of the comparison by the DRCV 470 being stored.
In the above processing, a write or read operation can be executed on the 1RW-RAM 300, in accordance with the test information provided from the PG 800.
Next, an exemplary operation of a march test which is one functional test for a RAM in the PG 800 and the 1RW-RAM circuit 200 will be described, with reference to FIGS. 10 and 11.
Firstly, in FIG. 10, 0 data is written to all addresses in the 1RW-RAM 300 in the ascending order for initialization (Steps A1 to A4; time t10 to t11 in FIG. 11).
Specifically, test information, namely, “address=zero address”, “data=L”, “we=H”, and “le=L” are set by the PG 800 (Step A1), and they are supplied to the 1RW-RAM 300, i.e., the 1RW-RAM circuit 200 (Step A2). Then, it is determined by the PG 800 whether or not the “address” is the last address, e.g., “1023” (Step A3). If the “address” is not the last address (the No route from Step A3), the “address” is incremented by one (Step A4), and the flow transitions to Step A2.
Otherwise, if the “address” is the last address (the Yes route from Step A3), the 0 data written during the initialization is read and 1 data is written, for all addresses in the ascending order (Steps A5 to A11; time t11 to t12 in FIG. 11).
Specifically, test information, namely, “address=zero address (0)” (Step A5), “data=L”, “we=L”, and “le=H” (Step A6) are set by the PG 800, and are supplied to the 1RW-RAM 300 (Step A7). Subsequently, test information, namely, “data=H”, “we=H”, and “le=L” are set by the PG 800 (Step A8), and are supplied to the 1RW-RAM 300 (Step A9). Then, it is determined by the PG 800 whether or not the “address” is the last address (Step A10). If the “address” is not the last address (the No route from Step A10), the “address” is incremented by one (Step A11), and the flow transitions to Step A6.
Otherwise, if the “address” is the last address (the Yes route from Step A10), the 1 data written in Steps A5 to A11 is read and 0 data is written, for all addresses in the descending order (Steps A12 to A18; time t12 to t13 in FIG. 11).
Specifically, test information, namely, “address=last address” (Step A12), “data=H”, “we=L”, and “le=H” (Step A13) are set by the PG 800, and are supplied to the 1RW-RAM 300 (Step A14). Subsequently, test information, namely, “data=L”, “we=H”, and “le=L” are set by the PG 800 (Step A15), and are supplied to the 1RW-RAM 300 (Step A16). Then, it is determined by the PG 800 whether or not the “address” is the zero address (Step A17). If the “address” is not the zero address (the No route from Step A17), the “address” is decremented by one (Step A18), and the flow transitions to Step A13.
Otherwise, if the “address” is the zero address (the Yes route from Step A17), the 0 data written in Steps A12 to A18 is read, for all addresses in the descending order (Steps A19 to A22; time t13 to t14 in FIG. 11).
Specifically, test information, namely, “address=last address”, “data=L”, “we=L”, and “le=H” are set by the PG 800 (Step A19), and are supplied to the 1RW-RAM 300 (Step A20). Then, it is determined by the PG 800 whether or not the “address” is the zero address (Step A21). If the “address” is not the zero address (the No route from Step A21), the “address” is decremented by one (Step A22), and the flow transitions to Step A20. Otherwise, if the “address” is the zero address (the Yes route from Step A21), the processing is terminated.
In the above flow, a march test is executed wherein 0 and 1 data are written and read for the 1RW-RAM 300 in the ascending and descending orders.
Next, the integrated circuit 110 depicted in FIG. 7 will be described in detail.
FIG. 12 is a diagram illustrating a detailed exemplary configuration of an integrated circuit 110 including a 1R1W-RAM circuit 210, and FIG. 13 is a flowchart illustrating an exemplary operation of a 1R1W-RAM circuit 210.
FIGS. 14 and 15 are flowcharts illustrating an exemplary operation of a march test on the test control circuit 810 for the 1R1W-RAM, and FIG. 16 is a diagram illustrating an exemplary operation of the 1R1W-RAM circuit 210 in the march test.
In (a) of FIG. 16, the vertical axis indicates address in a 1R1W-RAM 310, whereas the horizontal axis indicates time. Further, “W0” and “W1” indicate write of 0 data and 1 data, respectively, “R0” and “R1” indicate read of 0 data and 1 data, respectively. The numbers (1) to (10) in the timing chart in (b) of FIG. 16 indicate corresponding signals or registers in FIG. 12.
As illustrated in FIG. 12, the integrated circuit 110 includes n 1R1W-RAM circuits 210-1 to 210-n, and a PG for a 1R1W-RAM as an example of a test control circuit (hereinafter, simply referred to as a PG) 810. Hereinafter, any one of the 1R1W-RAM circuits may be simply referred to as a 1R1W-RAM circuit 210.
In the integrated circuit 110, a single PG 810 is connected to the multiple 1R1W-RAM circuits 210, test information is output from the PG 810 to each of the 1R1W-RAM circuits 210.
The 1R1W-RAM circuit 210 includes a 1R1W-RAM 310 to be tested, and a BIST circuit 400B added to the 1R1W-RAM 310.
As described above, unlike the 1RW-RAM 300, the 1R1W-RAM 310 illustrated in FIG. 12 is a RAM which allows simultaneous write and read operations, and includes two address input terminals, namely, a 10-bits write address terminal “WA” and a read address terminal “RA”. The 1R1W-RAM 310 further includes a 1-bit write enable terminal “WE” for controlling write operations, a read enable terminal “RE” for controlling read operations, a 72-bits data input terminal and a data output terminal.
If an input signal to the “WE” terminal is “H”, the 1R1W-RAM 310 writes a cell selected by the write address, and if an input signal to the “RE” terminal is “H”, the 1R1W-RAM 310 reads a cell selected by the read address. The addresses input to the “WA” and “RA” terminals are maintained to be different, for the purpose of protecting the circuit in the 1R1W-RAM 310.
Write and read operations in the 1R1W-RAM 310 are executed one clock after when input signals, i.e., a write or read address signal, a write or read enable signal, and a data signal, are supplied from the test control circuit 810.
The 1R1W-RAM 310 illustrated in FIG. 12 includes a configuration of 1024 words×72 bits, as the 1RW-RAM 300 illustrated in FIG. 8.
In a test for checking the functions of the 1R1W-RAM 310, a write and a read are simultaneously executed to check whether they are successfully executed. Therefore, two address signals, i.e., for the write and the read, two data signals, i.e., for the write and the read (expected value), and two control signals for controlling write and read operations, are required.
The PG 810 for the 1R1W-RAM 310 generates a “write address” signal, a “read address” signal, a “write data” signal, a “read data” signal, and a “we” signal, an “re” signal, and an “le” signal, as test information, and supplies them to the 1R1W-RAM circuit 210.
The “write address” and “read address” signals are write address and read address signals to select a particular memory cell in the 1R1W-RAM 310, and the “write data” signal is write data to be written to the memory cell. The “read data” signal is an expected value for comparing against data read from the memory cell, and “re” signal is a read enable signal for enabling the read operation. The “we” and “le” signals are the same as those output from the PG 800 illustrated in FIG. 8.
The BIST circuit 400B includes registers 410, 415, 420, 425, 430, 435, 440, 450, and 460 that store test information supplied from the PG 810, and a DRCV 470 similar to that illustrated in FIG. 8.
Hereinafter, an exemplary operation of the 1R1W-RAM circuit 210 will be described with reference to FIG. 13.
Firstly, test information is generated by the PG 810 and is supplied to the 1R1W-RAM circuit 210, and the “write address” signal is stored to the WA 420, the “write data” signal to the WD 430, the “we” signal to the +WE 410, the “read address” signal to the RA 425, the “read data” signal to the RD 435, the “re” signal to the +RE 415, and the “le” signal to the +LE 440 (Step S210).
Next, in the BIST circuit 400B, an “RD” signal which is an output from the RD 435 is stored in an RD_delayed 450, and a “+LE” signal which is an output from the +LE 440 is stored in +LE_delayed 460 (Step S220).
Also in the BIST circuit 400B, it is determined whether or not a “+RE” signal which is an output from the +RE 415 is “H”, e.g., “1” (Step S230). If the “+RE” signal is “H” (the Yes route from Step S230), it is determined whether or not the “+WE” signal from the +WE 410 is “H” (Step S240).
If the “+WE” signal from the +WE 410 is “H” (the Yes route from Step S240), the “WD” signal from the WD 430 is written to a cell in the 1R1W-RAM 310 selected by the “WA” signal from the WA 420. Simultaneously with the write of the “WD” signal, a read is executed from a cell in the 1R1W-RAM 310 selected by the “RA” signal which is an output from the RA 425 (Step S250).
Subsequently, in the BIST circuit 400B, it is determined whether or not the value of a “+en” signal which is an output from the +LE_delayed 460 is “H” (Step S260). If the “+en” signal is “H” (the Yes route from Step S260), a “Read data” signal which is read data from the 1R1W-RAM 310 is compared against an “RD_delayed” signal which is an output from the RD_delayed 450, i.e., the expected value, in the DRCV 470, and the result is saved (Step S270). Otherwise, if the “+en” signal is “L” (the No route from Step S260), the processing in Step S270 is deterred.
Otherwise, if the “+WE” signal from the +WE 410 is “L”, e.g., “0” in Step S240 (the No route from Step S240), a read is executed from a cell in the 1R1W-RAM 310 selected by the “RA” signal from the RA 425 (Step S280) and the flow proceeds to the processing in Step S260.
If “+RE” signal from the +RE 415 is “L” in Step S230 (the No route from Step S230), it is determined whether or not the “+WE” signal from the +WE 410 is “H” (Step S290). If the “+WE” signal is “H” (the Yes route from Step S290), the “WD” signal from the WD 430 is written to a cell in the 1R1W-RAM 310 selected by the “WA” signal from the WA 420 (Step S300) and the flow proceeds to the processing in Step S260. Otherwise, if the “+WE” signal is “L” (the No route from Step S290), the processing in Step S300 is deterred and the flow proceeds to the processing in Step S260.
In this case, the processing in Step S220 is executed to synchronize the timing of the expected value supplied from the PG 810 with the timing of the “Read data” from the 1R1W-RAM 310, when the cell in the 1R1W-RAM 310 is read in Step S250 or S280.
In other words, the RD_delayed 450 is a register that delays the “RD” signal from the RD 435 by one clock cycle required for the read operation of the 1R1W-RAM 310, for the comparison by the DRCV 470 in Step S270. Similarly, the +LE_delayed 460 is a register that delays the “+LE” signal from the +LE 440 by one clock cycle, in order to wait for the result of the comparison by the DRCV 470 being stored.
In the above processing, write and/or read operation(s) can be executed on the 1R1W-RAM 310, in accordance with the test information provided from the PG 810.
Next, an exemplary operation of a march test on the PG 810 and the 1R1W-RAM circuit 210 will be described with reference to FIGS. 14 to 16.
Firstly, in FIG. 14, 0 data is written to all addresses in the 1R1W-RAM 310 in the ascending order for initialization, simultaneously with read (Steps B1 to B4; time t20 to t21 in FIG. 16).
Specifically, test information, namely, “write address=zero address (0)”, “write data=L”, “we=H”, “read address=zero address”, “read data=L”, “re=L”, and “le=L”, is set by the PG 810 (Step B1), and are supplied to the 1R1W-RAM 310, i.e., the 1R1W-RAM circuit 210 (Step B2). Then it is determined by the PG 810 whether or not the “write address” is the last address, e.g., “1023” (Step B3). If the “write address” is not the last address (the No route from Step B3), the “write address” is incremented by one and “read address=write address−1”, “re=H”, and “le=H” are set (Step B4) and the flow transitions to Step B2.
Thus, in Steps B1 to B4, in order to execute a read test simultaneously with a write, upon writing “write address=1 address”, a read is executed from “read address=write address−1”, i.e., the zero address and such a simultaneous read is repeated until the “read address” reaches the last address−1.
Otherwise, if the “address” is the last address (the Yes route from Step B3), the 0 data written during the initialization is read and 1 data is written, for all addresses in the ascending order (Steps B5 to B14; time t21 to t22 in FIG. 16).
Specifically, test information, namely, “write address=zero address”, “read address=zero address”, “write data=H”, “re=H”, and “le=H” (Step B5), and “we=L” and “read data=L” (Step B6) are set by the PG 810, and are supplied to the 1R1W-RAM 310 (Step B7). Then “we=H” is set (Step B8), and it is determined whether or not the “write address” is the zero address by the PG 810 (Step B9). If the “write address” is not the zero address (the No route from Step B9), “read data=H” and “read address=write address−1” are set (Step B10), and are supplied to the 1R1W-RAM 310 (Step B12). Otherwise, if the “write address” is the zero address (the Yes route from Step B9), “read data=L” and “read address=last address” are set (Step B11) and the flow transitions to Step B12.
Once Step B12 is executed, it is determined by the PG 810 whether or not the “write address” is the last address (Step B13). If the “write address” is not the last address (the No route from Step B13), the “write address” is incremented by one and “read address=write address” is set (Step B14) and the flow transitions to Step B6. Otherwise, if the “write address” is the last address (the Yes route from Step B13), the flow transitions to “X” in FIG. 15.
As described above, in Steps B5 to B14, for executing a simultaneous read test, a read is executed from the “read address=last address” if the “write address=zero address”, otherwise, from the “read address=write address−1”. Such a simultaneous read is repeated until the “read address” reaches last address−1.
Once transitioned to “X” in FIG. 15, the 1 data written in Steps B5 to B14 is read and 0 data is written, for all addresses in the descending order (Steps B15 to B24; time t22 to t23 in FIG. 16).
Specifically, test information, namely, “write address=last address”, “read address=last address”, “write data=L”, “re=H”, and “le=H” (Step B15), and “we=L” and “read data=H” (Step B16) are set by the PG 810, and are supplied to the 1R1W-RAM 310 (Step B17). Then “we=H” is set (Step B18), and it is determined whether or not the “write address” is the last address by the PG 810 (Step B19). if the “write address” is not the last address (the No route from Step B19), “read data=L” and “read address=write address+1” are set (Step B20), and are supplied to the 1R1W-RAM 310 (Step B22). Otherwise, if the “write address” is the last address (the Yes route from Step B19), “read data=H” and “read address=zero address” are set (Step B21) and the flow transitions to Step B22.
Once Step B22 is executed, it is determined by the PG 810 whether or not the “write address” is the zero address (Step B23). If the “write address” is not the zero address (the No route from Step B23), the “write address” is decremented by one and “read address=write address” is set (Step B24) and the flow transitions to Step B16.
As described above, in Steps B15 to B24, for executing a simultaneous read test, a read is executed from the “read address=zero address” if the “write address=last address”, otherwise, from the “read address=write address+1”. Such a simultaneous read is repeated until the “read address” reaches 1.
Otherwise, if the “address” is the zero address (the Yes route from Step B23), the 0 data written in Steps B15 to B24 is read, for all addresses in the descending order (Steps B25 to B28; time t23 to t24 in FIG. 16).
Specifically, test information, namely, “read address=last address”, “read data=L”, “re=H”, and “le=H” are set by the PG 810 (Step B25), and are supplied to the 1R1W-RAM 310 (Step B26). Then, it is determined by the PG 810 whether or not the “read address” is the zero address (Step B27). If the “read address” is not the zero address (the No route from Step B27), the “read address” is decremented by one (Step B28), and the flow transitions to Step B26. Otherwise, if the “read address” is the zero address (the Yes route from Step B27), the processing is terminated.
A simultaneous read test is not executed in Steps B25 to B28 since no write is executed.
In the above flow, a march test is executed wherein 0 and 1 data are written and read, and a simultaneous read test is executed upon write is executed in the ascending and descending orders, for the 1R1W-RAM 310.
Note that, in a related art for generating test signals, multiple physically distinct memories include respective logic blocks, each of which receives a common input supplied from a state machine for specifically testing the memory.
In another related art, in a first operation mode, a circuit that controls write of data to a semiconductor memory, and a circuit that controls read of data from the semiconductor memory are operated on clock signals which are asynchronous from each other, whereas in a second operation mode, they are operated on clock signals which are synchronized from each other.
Patent Reference 1: Japanese Laid-Open Patent Publication No. H10-40700
Patent Reference 2: Japanese Laid-open Patent Publication No. 2005-235259
As illustrated in FIGS. 7 and 12, in order to execute a BIST on a 1R1W-RAM, two sets of address, data, and control signal supplied from a test control circuit are required.
In addition, in a functional test of a 1R1W-RAM, for executing simultaneous write and read operations, which are unique to the 1R1W-RAM, an additional function is required to a test control circuit, if the test control circuit is for a 1RW-RAM. If both 1RW-RAMs and 1R1W-RAMs are present in an integrated circuit, dedicated test control circuits are required for the respective RAMs.
Further, the signal line count distributed to each of 1R1W-RAMs in integrated circuit from test control circuit is doubled as compared to the signal line count for 1RW-RAMs, and the quantities of wires and buffers used for signal distribution are also doubled.
In addition, in the above-described related art wherein a logic block is provided to each memory, one of address bits generated for a first port is inverted in a local logic circuit to generate an address to a second port, for testing a dual port RAM. However, in this technique, expected data must be modified since an address intersection arises in the addresses for the first and second port, which results in an increase in the circuit size and the manufacturing cost of the logic circuit.
As described above, the circuit size and the manufacturing cost are increased in an integrated circuit including a 1R1W-RAM (storing unit) and a BIST circuit (tester) that tests the 1R1W-RAM, as compared to an integrated circuit including a 1RW-RAM and a BIST circuit.